Integrated circuits are typically fabricated from one or more layers of different materials. Typical integrated circuits include multiple interconnected patterned metal layers, with intervening inter-level dielectric (ILD) layers to electrically insulate the metal layers.
The selection of a specific ILD depends upon the performance, density and reliability requirements of a particular semiconductor circuit. Ideal ILDs are contamination and defect free, exhibit a low dielectric constant that approaches unity, have a sufficiently high field strength, provide a good barrier to sodium ions (Na+) and provide infinite etch selectivity to underlying materials, such as silicides, silicon and polysilicon. ILDs must also conform to different topographies, such as steps and gaps, exhibit good adhesion to the underlying and overlying layers and be capable of planarization.
Good ILD planarization characteristics become increasingly important as the number of layers in a device increases because photolithography processes are acutely sensitive to variations in ILD topography, particularly in patterning vias. However, in fabricating ultra high density semiconductor devices, which include tightly packed, high aspect ratio metal patterns, it can be difficult to satisfactorily planarize a deposited dielectric material, particularly when the dielectric material is deposited globally on both relatively dense areas containing a relatively large number of circuit components and other areas such as peripheral circuitry regions that contain relatively few circuit components.
A prior conventional approach to forming ILDs involves depositing two dielectric layers. First, a first gap filling layer, e.g., spin-on-glass (SOG), silicon dioxide (SiO.sub.2), or other oxide, is deposited on a patterned metal layer to fill any gaps therein. Typical gap fill layers not only fill gaps but also deposit on the upper surface of underlying patterned metal feature. Then a second dielectric layer, referred to as a "cap layer," is deposited on the gap fill layer. The cap layer is then planarized (leveled), as by a chemical-mechanical polishing (CMP), to provide a substantially flat upper surface on which additional layers are formed. Such a technique is illustrated in FIGS. 1A through 1C.
Referring to FIG. 1A, a conventional integrated circuit structure is designated by the reference numeral 100. A dielectric layer 102, typically, silicon dioxide (SiO).sub.2, is formed on a substrate 104, typically doped monocrystalline silicon (Si). A patterned metal layer comprising one or more metal features or "stacks" 105 with gaps therebetween, is formed on dielectric layer 102. Conventional metal stacks 105 comprise a lower barrier layer 106, typically titanium (Ti), an intermediate primary conductive layer 108, typically aluminum (Al), on barrier layer 106, and an upper anti-reflective coating (ARC) 110, typically titanium-nitride (TiN), on conductive layer 108. Barrier layer 106 and ARC 110 tend to reduce electromigration in conductive layer 108, albeit at the cost of increasing sheet resistance. The total height of metal stacks 105 varies depending upon the particular application, but is typically about one micron.
Once metal stacks 105 have been formed, a dielectric gap fill layer 112, such as SiO.sub.2, is deposited on dielectric layer 102 and ARC 110, to insulate metal stacks 105 from each other. Gap fill layer 112 characteristically forms peaks 114 on top of metal stacks 105 whose height 115, 116 above the upper surface of ARC 110 varies depending upon both the width of metal stacks 105 and the particular gap fill material and deposition process.
As illustrated in FIG. 1B, a dielectric cap layer 118, such as SiO.sub.2, is deposited on gap fill layer 112. Dielectric cap layer 118 may be the same material as gap fill layer 112, or may be a different material. Cap layer 118 typically has a thickness of about 1.2 to about 1.8 microns. The upper surface 120 of dielectric cap layer 118 is not flat, but generally conforms to the shape of gap fill layer 112. As illustrated in FIG. 1C, dielectric cap layer 118 is then planarized as by CMP, so its upper surface 120 is substantially flat. During conventional planarization of cap layer 118 about 0.2 to about 0.8 microns of dielectric material must be removed to achieve adequate planarity, leaving a cap layer 118 having a thickness of about one micron. Thus, gap fill layer 112 and cap layer 118 form an ILD 122 having a substantially flat upper surface 120 upon which additional integrated circuit layers may be formed.
The conventional methodology illustrated in FIGS. 1A-1C suffers from drawbacks, particularly as miniaturization drives design features in to the deep sub-micron range, e.g., about 0.18 .mu. and under. Specifically, it is sometimes difficult to obtain a substantially flat upper ILD surface using conventional CMP when the underlying topography contains relatively large steps and height variations. Conventional practices remove a predetermined amount of material which is estimated to be sufficient to provide a substantially flat planar upper ILD surface. However, this often requires deposition of a relatively thick cap layer 118, thereby undesirably increasing material processing costs.
More importantly, conventional ILD structures, such as the ILD structure 100 illustrated in FIGS. 1A-1C, often suffer from poor immunity to hot carrier injection (HCI) reliability failures. It is recognized that HCI problems typically arise when semiconductor device dimensions are reduced while maintaining the supply voltage at the same level, thereby increasing the electric field generated in the silicon substrate, and consequently sufficiently energizing electrons in the channel so that they are injected into the gate oxide, thereby changing the gate oxide, causing long term device degradation by causing the threshold voltage of the device and reducing its transconductance.
Another problem attendant upon conventional practices stems from the permeation of hydrogen atoms from gap fill layer 112 through dielectric layer 102, adversely affecting underlying devices, particularly when employing hydrogen silsesquioxane (HSQ) as the material for the gap fill layer.
Accordingly, there is a need for integrated circuits having ILDs that avoid the problems and limitations of prior approaches. There is a particular need for integrated circuits having ILDs that can be planarized to provide a substantially flat upper surface while eliminating a substantially preventing hot carrier degradation.